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Artigo de periodico
ISFET fabrication and characterization for hydrogen peroxide sensing (2023)
Duarte, Pedro Henrique; Rangel, Ricardo Cardoso; Ramos, Daniel Augusto; Yojo, Leonardo Shimizu; Mori, Carlos Augusto Bergfeld; Sasaki, Katia Regina Akemi; Agopian, Paula Ghedini Der ; Martino, João Antonio
Source: Journal of Integrated Circuits and Systems. Unidade: EP
Subjects: TRANSISTORES, SOLUÇÕES
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
DUARTE, Pedro Henrique et al. ISFET fabrication and characterization for hydrogen peroxide sensing. Journal of Integrated Circuits and Systems, v. 18, n. 1, p. 1-4, 2023Tradução . . Disponível em: https://doi.org/10.29292/jics.v18i1.646. Acesso em: 28 abr. 2024.
APA
Duarte, P. H., Rangel, R. C., Ramos, D. A., Yojo, L. S., Mori, C. A. B., Sasaki, K. R. A., et al. (2023). ISFET fabrication and characterization for hydrogen peroxide sensing. Journal of Integrated Circuits and Systems, 18( 1), 1-4. doi:10.29292/jics.v18i1.646
NLM
Duarte PH, Rangel RC, Ramos DA, Yojo LS, Mori CAB, Sasaki KRA, Agopian PGD, Martino JA. ISFET fabrication and characterization for hydrogen peroxide sensing [Internet]. Journal of Integrated Circuits and Systems. 2023 ; 18( 1): 1-4.[citado 2024 abr. 28 ] Available from: https://doi.org/10.29292/jics.v18i1.646
Vancouver
Duarte PH, Rangel RC, Ramos DA, Yojo LS, Mori CAB, Sasaki KRA, Agopian PGD, Martino JA. ISFET fabrication and characterization for hydrogen peroxide sensing [Internet]. Journal of Integrated Circuits and Systems. 2023 ; 18( 1): 1-4.[citado 2024 abr. 28 ] Available from: https://doi.org/10.29292/jics.v18i1.646
Trabalho de evento
Improvement of Retention Time Using Pulsed Back Gate Bias on UTBOX SOI Memory Cell (2013)
Martino, João Antonio ; Sasaki, Katia Regina Akemi; Nissimoff, Albert; Almeida, Luciano Mendes; Aoulaiche, Marc; Simoen, Eddy ; Claeys, Cor
Source: EUROSOI 2013. Conference titles: European Workshop on Silicon on Insulator Technology, Devices and Circuits. Unidade: EP
Assunto: MICROELETRÔNICA (CONGRESSOS)
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MARTINO, João Antonio et al. Improvement of Retention Time Using Pulsed Back Gate Bias on UTBOX SOI Memory Cell. 2013, Anais.. Paris: Institut Superieur d'Électronique, 2013. . Acesso em: 28 abr. 2024.
APA
Martino, J. A., Sasaki, K. R. A., Nissimoff, A., Almeida, L. M., Aoulaiche, M., Simoen, E., & Claeys, C. (2013). Improvement of Retention Time Using Pulsed Back Gate Bias on UTBOX SOI Memory Cell. In EUROSOI 2013. Paris: Institut Superieur d'Électronique.
NLM
Martino JA, Sasaki KRA, Nissimoff A, Almeida LM, Aoulaiche M, Simoen E, Claeys C. Improvement of Retention Time Using Pulsed Back Gate Bias on UTBOX SOI Memory Cell. EUROSOI 2013. 2013 ;[citado 2024 abr. 28 ]
Vancouver
Martino JA, Sasaki KRA, Nissimoff A, Almeida LM, Aoulaiche M, Simoen E, Claeys C. Improvement of Retention Time Using Pulsed Back Gate Bias on UTBOX SOI Memory Cell. EUROSOI 2013. 2013 ;[citado 2024 abr. 28 ]
Trabalho de evento
Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices (2013)
Martino, João Antonio ; Nicoletti, Talitha; Sasaki, Katia Regina Akemi; Aoulaiche, Marc; Simoen, Eddy ; Claeys, Cor
Source: EUROSOI 2013. Conference titles: European Workshop on Silicon on Insulator Technology, Devices and Circuits. Unidade: EP
Assunto: MICROELETRÔNICA (CONGRESSOS)
A citação é gerada automaticamente e pode não estar totalmente de acordo com as normas
ABNT
MARTINO, João Antonio et al. Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices. 2013, Anais.. Paris: Institut Superieur d'Électronique, 2013. . Acesso em: 28 abr. 2024.
APA
Martino, J. A., Nicoletti, T., Sasaki, K. R. A., Aoulaiche, M., Simoen, E., & Claeys, C. (2013). Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices. In EUROSOI 2013. Paris: Institut Superieur d'Électronique.
NLM
Martino JA, Nicoletti T, Sasaki KRA, Aoulaiche M, Simoen E, Claeys C. Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices. EUROSOI 2013. 2013 ;[citado 2024 abr. 28 ]
Vancouver
Martino JA, Nicoletti T, Sasaki KRA, Aoulaiche M, Simoen E, Claeys C. Experimental and Simulation of 1T-DRAM Trend with the Gate Length on UTBOX Devices. EUROSOI 2013. 2013 ;[citado 2024 abr. 28 ]

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